Intersil Corporation Staff Design Verification Engineer in Austin, Texas

Staff Design Verification Engineer

Location USA - TX - Austin

Employment duration Full time

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Intersil, a Renesas Company, is a leading provider of innovative power management and precision analog solutions. The company's products form the building blocks of increasingly intelligent, mobile and power hungry electronics, enabling advances in power management to improve efficiency and extend battery life. With a deep portfolio of intellectual property and a rich history of design and process innovation, Intersil is the trusted partner to leading companies in some of the world's largest markets, including industrial and infrastructure, mobile computing, automotive and aerospace. For more information about Intersil or to find out how to become a member of our winning team, visit our careers page on LinkedIn at https://www.linkedin.com/company/intersil/careers?trk=topnavcareers

In this role you will perform design verification of mixed signal ICs for the digital power market.

Requirements:

  • 7+ years of experience in design verification in Verilog or systemVerilog environment

  • Experience with mixed-signal SOC designs with industry-leading embedded MCUs

  • Directed test expertise with some UVM and assertion generation

  • Ability to develop verification infrastructure and reporting tools

  • Strong written and verbal communications skill required for rapid bug closure

Desired skills/experience:

  • SystemVerilog modeling for analog and mixed-signal blocks

  • Firmware (C language) based test routines to run on embedded MCU

  • Perl/python script development

  • Coverage metrics definition and coverage model development based on marketing and design specifications

  • I2C and/or PMBus communication protocol

  • High-speed serial interfaces

This company is an equal opportunity employer and makes employment decisions without regard to race, gender, disability or protected veteran status.